A logic network of a circuit may be analyzed to identify timing problems in the design of a circuit. A single hold analysis violation that manifests in silicon can cause a functional failure, rendering the product unusable. A thorough analysis and resolution of all potential hold failures is therefore critical to the viability of the final product. When a particular place in a design exhibits a hold race, (a violation of the hold analysis), tens of thousands of similar paths could be related to this same electrical failure. Determining the most optimal location to insert delay cells to address all failures is challenging and resource intensive.
Design engineers must add enough delay cells within a path to slow down the data in order to meet the hold requirement of the downstream flop, but must avoid putting too many delay cells in, which may violate the setup requirements of the path and related paths. There is a balance between having just the right amount of logic to meet the hold requirements and not breaking the timing requirements.
There may be several ways to insert delay cells to fix hold failures and not violate setup timing requirements. However, some possible solutions may adversely impact power if too many delay cells are inserted into a design.
There is a need to address situations where there is a hold race, and to provide automated feedback to design engineers to enable a solution which optimizes a balance in delay, power, and electrical robustness. Currently, there is a need to identify an optimal set and location of points to address hold analysis in a structure custom cell-based design.